Definition of the best strategy for buffer control of a multistream ultra low delay HDTV codec
Nowadays television standards are evolving towards high-definition. However, the arrival of the high-definition poses higher requirements onto the underlying technology, e.g. FPGA. With this requirements near the hardware limits, the singlestream approach is no longer feasible at an affordable cost.
Therefore, a parallelization technique, referred as multistream approach, where the input data is spatially partitioned before encoding, converting an HDTV sequence into multiple SDTV sequences, each of them being encoded in parallel to obtain multiple encoded bitstreams. The decoder consists of multiple decoding units that reconstruct the original SDTV sequences and a spatial joining unit that reverts the encoder partition schema giving the decoded HDTV sequence.
Furthermore, some video codec have specific targets that require them to work in real-time. This new constrain will affect mainly the rate buffer size due to its main contribution to total encoding delay. For a real-time operation, a low delay upper bound is fixed, which greatly reduces the rate buffer size making it much more sensible to bitrate changes and prone to overflow or underflow. In order to avoid overflowing and underflowing, a new rate control strategy, that takes into consideration the new codec environment and target, has been developed.
First part of the project:
Contact: Harish Reddy Chinta Reddy and Rajesh Babu Chunduri
Report: .pdf file
Second part of the project:
Contact: Lluch Parellada Oriol
Report: .pdf file
Virtual Memory support for MPEG-4 Accelerators on FPGA
This platform has been created to aid in the rapid emulation, test, and verification of FPGA designs for complex multimedia standards. It addresses the data communications and controls signal exchanges between a host computer system and a reconfigurable FPGA co-processor based on the concept of virtual socket.
The goal of this project was to propose a virtual memory interface as an extension of an existing framework so that any hardware accelerator into the FPGA can access any data from the main memory of the host computer. The hardware accelerator has no idea where the data are physically or how they flow through the different ports and buses. The hardware accelerators access data thanks to virtual adresses. The Virtual Memory Extension provides to the hardware accelerators the virtual memory abstraction and shared address space with user software.
Contact: Christophe Lucarz