All Publications

Journal Articles

2018

S. Casale-Brunet; M. Mattavelli : Execution Trace Graph of Dataflow Process Networks; Ieee Transactions On Multi-Scale Computing Systems. 2018-07-01. DOI : 10.1109/TMSCS.2018.2790921.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs; IEEE Transactions on Multi-Scale Computing Systems. 2018. DOI : 10.1109/TMSCS.2017.2774294.

2017

Y. Guo; S. Schütz; A. Vaghi; Y.-H. Li; Z. Guo et al. : Stand-Alone Stretchable Absolute Pressure Sensing System for Industrial Applications; IEEE Transactions on Industrial Electronics. 2017. DOI : 10.1109/TIE.2017.2701763.
D. R. Barrettino : Smart Contact Lenses and Eye Implants Could Provide Medical Insights; IEEE Spectrum. 2017.

2016

E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck : Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016-08-02. DOI : 10.1109/TCAD.2016.2597215.
K. Jerbi; H. Yviquel; A. Sanchez; D. Renzi; D. J. De Saint Jorre et al. : On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling; Journal of Signal Processing Systems. 2016-03-05. DOI : 10.1007/s11265-016-1113-x.
I. Numanagic; J. K. Bonfield; F. Hach; J. Voges; J. Ostermann et al. : Comparison of high-throughput sequencing data compression tools; Nature Methods. 2016. DOI : 10.1038/nmeth.4037.
M. Michalska; N. Zufferey; M. Mattavelli : Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs; Journal Of Electrical And Computer Engineering. 2016. DOI : 10.1155/2016/8536432.

2015

C. Massimo; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck : Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies; Journal of Signal Processing Systems. 2015. DOI : 10.1007/s11265-015-1083-4.
C. Sau; P. Meloni; L. Raffo; F. Palumbo; E. Bezati et al. : Automated Design Flow for Multi-Functional Dataflow-Based Platforms; Journal of Signal Processing Systems -Signal Image and Video Technology-. 2015. DOI : 10.1007/s11265-015-1026-0.
A. Prihozhy; E. Bezati; A. A.-H. Ab Rahman; M. Mattavelli : Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. DOI : 10.1109/TCAD.2015.2427278.
J. Boutellier; J. Ersfolk; J. Lilius; M. Mattavelli; G. Roquier et al. : Actor Merging for Dataflow Process Networks; Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2411229.

2014

M. Canale; S. Casale-Brunet : A Multidisciplinary Approach for Model Predictive Control Education: A Lego Mindstorms NXT-based Framework; International Journal Of Control Automation And Systems. 2014. DOI : 10.1007/s12555-013-0282-7.
E. Bezati; R. Thavot; G. Roquier; M. Mattavelli : High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms; Journal Of Real-Time Image Processing. 2014. DOI : 10.1007/s11554-013-0326-5.

2013

S. Casale-Brunet; A. Elguindy; E. Bezati; R. Thavot; G. Roquier et al. : Methods to explore design space for MPEG RMC codec specifications; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.012.
E. S. Jang; M. Mattavelli; M. Preda; M. Raulet; H. Sun : Reconfigurable media coding: An overview; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.008.
M. Grafl; C. Timmerer; H. Hellwagner; G. Xilouris; G. Gardikis et al. : Scalable Media Coding Enabling Content-Aware Networking; IEEE Multimedia. 2013. DOI : 10.1109/MMUL.2012.57.
J. J. Ahmad; S. Li; R. Thavot; M. Mattavelli : Secure Computing with the MPEG RVC Framework; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.015.

2012

G. Roquier; E. Bezati; M. Mattavelli : Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs; Journal of Electrical and Computer Engineering, Special issue on "ESL Design Methodology". 2012. DOI : 10.1155/2012/484962.

2011

A. Rahman; A. A. H. Bin; A. Prihozhy; M. Mattavelli : Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL; Eurasip Journal on Image and Video Processing. 2011. DOI : 10.1186/1687-5281-2011-19.

2010

M. Mattavelli; I. Amer; M. Raulet : The reconfigurable video coding standard; IEEE Signal Processing Magazine. 2010. DOI : 10.1109/MSP.2010.936032.

2009

I. Amer; C. Lucarz; G. Roquier; M. Mattavelli; M. Raulet et al. : Reconfigurable Video coding on Multicore An overview of its main objectives; Ieee Signal Processing Magazine. 2009. DOI : 10.1109/MSP.2009.934107.
Y.-K. Chen; G. G. (. Lee; M. Mattavelli; E. S. Jang : Special Issue: Algorithm/Architecture Co-Exploration of Visual Computing on Emerging Platforms; Ieee Transactions On Circuits And Systems For Video Technology. 2009. DOI : 10.1109/TCSVT.2009.2034438.
M. Raulet; M. Mattavelli; J. Janneck : Guest Editorial: Special Issue on Reconfigurable Guest Editorial: Special Issue on Reconfigurable Video Coding; Journal of Signal Processing Systems. 2009. DOI : 10.1007/s11265-009-0418-4.
R. Zhou; J. D. Reiss; M. Mattavelli; G. Zoia : A Computationally Efficient Method for Polyphonic Pitch Estimation; EURASIP Journal on Advances in Signal Processing. 2009. DOI : 10.1155/2009/729494.
G. G. (. Lee; Y.-K. Chen; M. Mattavelli; E. S. Jang : Algorithm/Architecture Co-Exploration of Visual Computing: Overview and Future Perspectives; IEEE Transactions On Circuits And Systems For Video Technology. 2009. DOI : 10.1109/TCSVT.2009.2031376.
G. G. (. Lee; Y.-K. Chen; M. Mattavelli; E. S. Jang : An Introduction to the Special Issue on Algorithm/Architecture Co-Exploration of Visual Computing on Emerging Platforms; IEEE Transactions On Circuits And Systems For Video Technology. 2009. DOI : 10.1109/TCSVT.2009.2031376.
J. W. Janneck; I. D. Miller; D. B. Parlour; G. Roquier; M. Wipliez et al. : Synthesizing Hardware from Dataflow Programs; Journal of Signal Processing Systems. 2009. DOI : 10.1007/s11265-009-0397-5.
M. Wipliez; G. Roquier; J.-F. Nezan : Software Code Generation for the RVC-CAL Language; Journal of Signal Processing Systems. 2009. DOI : 10.1007/s11265-009-0390-z.
H. Aman-Allah; K. Maarouf; E. Hanna; I. Amer; M. Mattavelli : CAL Dataflow Components For an MPEG RVC AVC Baseline Encoder; Journal Of Signal Processing Systems For Signal Image And Video Technology. 2009. DOI : 10.1007/s11265-009-0399-3.
I. Amer; C. Lucarz; G. Roquier; M. Mattavelli; M. Raulet et al. : Reconfigurable Video Coding on Multicore: The Video Coding Standard for Multi-Core Platforms; IEEE SIGNAL PROCESSING MAGAZINE, Special issue on Multicore Platforms. 2009. DOI : 10.1109/MSP.2009.934107.
S. S. Bhattacharyya; J. Eker; J. Janneck; C. Lucarz; M. Mattavelli et al. : Overview of the MPEG Reconfigurable Video Coding Framework; Journal of Signal Processing Systems. 2009. DOI : 10.1007/s11265-009-0399-3.
J. Boutellier; C. Lucarz; S. Lafond; V. M. Gomez; M. Mattavelli : Quasi-Static Scheduling of CAL Actor Networks for Reconfigurable Video Coding; Journal of Signal Processing Systems, 2009. 2009. DOI : 10.1007/s11265-009-0389-5.
C. Lucarz; J. Piat; M. Mattavelli : Automatic synthesis of parsers and validation of bitstreams within the MPEG Reconfigurable Video Coding Framework; Journal of Signal Processing Systems. 2009. DOI : 10.1007/s11265-009-0395-7.

2008

M. Mattavelli; G. Zoia; R. Zhou : Music Onset Detection Based on Resonator Time Frequency Image; IEEE Transactions On Audio, Speech And Language Processing. 2008. DOI : 10.1109/TASL.2008.2002042.
M. Mattavelli; S. S. Bhattacharyya; J. Eker; C. von Platen; G. Brebner et al. : OpenDF – A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems; ACM SIGARCH Computer Architecture News, Special Issue: MCC08 – Multicore Computing 2008. 2008.
R. Mosqueron; J. Dubois; M. Mattavelli; D. Mauvilet : Smart camera based on embedded HW/SW coprocessor; Journal on Embedded Systems, EURASIP. 2008.

2007

I. Amer; W. Badawy; G. Jullien; M. Mattavelli; R. Turney : A Simplified 8 × 8 Transformation And Quantization Real-Time Ip-Block For MPEG-4 H.264/AVC Applications: A New Design Flow Approach; Journal of Circuits, Systems, and Computers . 2007. DOI : 10.1142/S021812660700399X.

2005

M. Ravasi; M. Matttavelli : High Abstraction Level Complexity Analysis and Memory Architecture Simulations for Multimedia Algorithms; IEEE Transactions on Circuits and Systems for Video Technology. 2005. DOI : 10.1109/TCSVT.2005.846414.

2001

F. Allah Cherigui; D. Mlynek : Low Energy Digit-serial Architectures for large GF(2m) multiplication; IEEE Proceedings - Circuits, Devices and Systems. 2001.
F. Allah Cherigui; D. Mlynek : Efficient Low-Energy, Digit-Serial Exponentiator for large Finite Field GF; IEEE Transactions on VLSI. 2001.

1999

L. Le Bourhis; G. Zoia; M. Mattavelli; D. Mlynek : An Efficient Host/Co-Processor Solution For Mpeg-4 Audio Composition; IEEE Transactions on Consumer Electronics. 1999. DOI : 10.1109/30.809221.

1998

M. Gumm; D. Mlynek : An Approach For Easy Handling And Interchanging Of Large VHDL-Based Design Databases For Simulation And Synthesis; Acad. Radiol.. 1998.

1995

L. Chaouat; A. Vachoux; D. Mlynek : An Expert Assistant for Hardware Systems Specification; High-level System Modeling: Specification and Design Methodologies. 1995.

Conference Papers

2018

A. A. Hernandez Lopez : Lossy compression of quality scores in differential gene expression: A first assessment and impact analysis. 2018. Data compression conference (DCC) , Snowbird, Utah, March 27-30, 2018.

2017

S. Casale-Brunet; E. Bezati; M. Mattavelli : Design space exploration of dataflow-based Smith-Waterman FPGA implementations, 2017 IEEE International Workshop on Signal Processing Systems (SiPS). 2017-10-03. Signal Processing Systems (SiPS), 2017 IEEE International Workshop on. p. 1-6. DOI : 10.1109/SiPS.2017.8109982.
M. Michalska; J. J. Ahmad; E. Bezati; S. Casale-Brunet; M. Mattavelli : Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). 2017-09-21. p. 1-8. DOI : 10.1109/PATMOS.2016.7833418.
M. Michalska; E. Bezati; S. Casale-Brunet; M. Mattavelli : Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms, 2017 25th European Signal Processing Conference (EUSIPCO). 2017-08-28. p. 1339-1343. DOI : 10.23919/EUSIPCO.2017.8081426.
S. Casale-Brunet; E. Bezati; M. Mattavelli : High level synthesis of Smith-Waterman dataflow implementations, 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). 2017-03-05. p. 1173-1177. DOI : 10.1109/ICASSP.2017.7952341.
D. Allegri; D. Vaca; D. Ferreira; M. Rogantini; D. R. Barrettino : Real-Time Monitoring of the Hydration Level by Multi-Frequency Bioimpedance Spectroscopy. 2017. IEEE International Instrumentation and Measurement Technology Conference, Torino, Italy, May 22-25, 2017. p. pp. 1-6.
M. Hernaez; C. Alberti; M. Mattavelli; I. Ochoa : MPEG-G the emerging standard for genomic data compression. 2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.
A. A. Hernandez-Lopez; J. Voges; C. Alberti; M. Mattavelli; J. Ostermann : Differential gene expression with lossy compression of quality scores in RNA-seq data. 2017. Data Compression Conference (DCC), Snowbird, UT, APR 04-07, 2017. p. 444-444. DOI : 10.1109/Dcc.2017.75.

2016

M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. Janneck : Trace-based manycore partitioning of stream-processing applications, 2016 50th Asilomar Conference on Signals, Systems and Computers. 2016-11-06. p. 422-426. DOI : 10.1109/ACSSC.2016.7869073.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : High-level system synthesis and optimization of dataflow programs for MPSoCs, 2016 50th Asilomar Conference on Signals, Systems and Computers. 2016-11-06. p. 417-421. DOI : 10.1109/ACSSC.2016.7869072.
M. Michalska; N. Zufferey; E. Bezati; M. Mattavelli : Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 217-224. DOI : 10.1109/MCSoC.2016.25.
S. Casale-Brunet; E. Bezati; M. Mattavelli : Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 289-296. DOI : 10.1109/MCSoC.2016.39.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 101-108. DOI : 10.1109/MCSoC.2016.23.
E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck : High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). 2016-07-17. p. 227-234. DOI : 10.1109/SAMOS.2016.7818352.
C. Alberti; N. Daniels; M. Hernaez; J. Voges; R. L. Goldfeder et al. : An Evaluation Framework for Lossy Compression of Genome Sequencing Quality Values. 2016. IEEE Data Compression Conference 2016, Snowbird, Utah, USA. DOI : 10.1109/Dcc.2016.39.

2015

R. Monnier; A. Mourelle; J.-P. Bernoux; C. Alberti; J. Le Feuvre et al. : H2B2VS (HEVC Hybrid Broadcast Broadband Video Services) – building innovative solutions over hybrid networks. 2015. International Broadcasting Conference 2015, Amsterdam, September 11, 2015.
M. Michalska; J. Boutellier; M. Mattavelli : A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures. 2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962-2966. DOI : 10.1016/j.procs.2015.05.498.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs. 2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443-1452. DOI : 10.1016/j.procs.2015.05.334.

2014

S. Casale Brunet; M. Michalska; E. Bezati; M. Mattavelli; J. Janneck et al. : TURNUS: an open-source design space exploration framework for dynamic stream programs. 2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014.
M. Canale; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck : Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, October 2014.
S. Casale Brunet; E. Bezati; M. Mattavelli; M. Canale; J. Janneck : Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014. DOI : 10.1109/DASIP.2014.7115623.
D. J. De Saint Jorre; D. Renzi; S. Casale Brunet; M. Michalska; E. Bezati et al. : MPEG high efficient video coding stream programming and many-cores scalability. 2014.
S. Casale-Brunet; M. Wiszniewska; E. Bezati; M. Mattavelli; J. W. Janneck et al. : TURNUS: An open-source design space exploration framework for dynamic stream programs. 2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.
S. Casale-Brunet; E. Bezati; M. Mattavelli; M. Canale; J. W. Janneck : Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.
E. Bezati; S. Casale Brunet; M. Mattavelli; J. W. Janneck : Coarse grain clock gating of streaming applications in programmable logic implementations. 2014. 2014 Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, 31 May - 1 June 2014. p. 1-6. DOI : 10.1109/ESLsyn.2014.6850387.
J. W. Janneck; S. Casale-Brunet; M. Mattavelli : Characterizing communication behavior of dataflow programs using trace analysis. 2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.
D. De Saint Jorre; C. Alberti; M. Mattavelli; S. Casale-Brunet : Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms. 2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.
J. W. Janneck; G. Cerdersjo; E. Bezati; S. C. Brunet : Dataflow machines. 2014. 2014 48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 2-5 November 2014. p. 1848-1852. DOI : 10.1109/ACSSC.2014.7094788.
M. Canale; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. W. Janneck : Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.
C. Sau; L. Raffo; F. Palumbo; E. Bezati; S. Casale-Brunet et al. : Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. 2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations. 2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014.
A. A.-H. Ab Rahman; S. Casale-Brunet; C. Alberti; M. Mattavelli : A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations. 2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.
J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. : ECMA-407: A New 3D audio codec implementation up to NHK 22.2. 2014. The 28th VDT International Convention 2014.
J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. : ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL. 2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.

2013

C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. : Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http. 2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63.
S. C. Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures. 2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182.
J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli : Modeling Control Tokens for Composition of CAL Actors. 2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.
J. Ersfolk; G. Roquier; W. Lund; M. Mattavelli; J. Lilius : STATIC AND QUASI-STATIC COMPOSITIONS OF STREAM PROCESSING APPLICATIONS FROM DYNAMIC DATAFLOW PROGRAMS. 2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620–2624.
S. Casale Brunet; C. Alberti; M. Mattavelli; J. Janneck : Systems Design Space Exploration by Serial Dataflow Program Executions. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.
S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.
S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Partitioning and Optimization of high level Stream applications for Multi Clock Domain Architectures. 2013. Signal Processing Systems (SiPS), Taipei, Taiwan, 16-18 October, 2013.
A. Rahman; A. A. H. Bin; S. Casale Brunet; C. Alberti; M. Mattavelli : Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study. 2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.
D. S. Jorre; D. Jack; C. Alberti; M. Mattavelli; S. Casale Brunet : Porting an MPEG-HEVC decoder to a low-power many-core platform. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.
E. Bezati; M. Mattavelli; J. Janneck : High-Level Synthesis of Dataflow Programs for Signal Processing Systems. 2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013.
M. Canale; S. Casale Brunet : A Lego Mindstorms NXT Experiment for Model Predictive Control Education. 2013. European Control Conference, Zurich, Switzerland, 2013.
S. Casale Brunet; E. Bezati; G. Roquier; C. Alberti; M. Mattavelli et al. : Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework. 2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : TURNUS: A design exploration framework for dataflow system design. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.
E. Bezati; S. Casale Brunet; M. Mattavelli; J. Janneck : Synthesis and optimization of high-level stream programs. 2013. lectronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : Buffer optimization based on critical path analysis of a dataflow program design. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.
E. Bezati; G. Roquier; M. Mattavelli : Live demonstration: High level software and hardware synthesis of dataflow programs. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS),, Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.
J. J. Ahmad; S. Li; M. Mattavelli : Performance Benchmarking of RVC based Multimedia Specifications. 2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems. 2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem. 2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : Representing Guard Dependencies in Dataflow Execution Traces. 2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.
C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. : Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP. 2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013.

2012

J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli : Scheduling of dynamic dataflow programs based on state space analysis. 2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661-1664.
C. Müller; D. Renzi; S. Lederer; S. Battista; C. Timmerer : Using Scalable Video Coding For Dynamic Adaptive Streaming Over HTTP in Mobile Environments. 2012. EUSIPCO12, Bucharest, Romania, 2012.08.31. p. 2208-2212.
M. Grafl; C. Timmerer; M. Waltl; D. Renzi; S. Battista et al. : Distributed Adaptation Decision-Taking Framework and Scalable Video Coding Tunneling for Edge and In-Network Media Adaptation. 2012. TEMU 2012, Heraklion, Greece, July 31, 2012. p. 6. DOI : 10.1109/TEMU.2012.6294710.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : Profiling of Dataflow Programs Using Post Mortem Causation Traces. 2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220-225. DOI : 10.1109/SiPS.2012.54.
A. Rahman; A. A. H. Bin; R. Thavot; S. Casale Brunet; E. Bezati et al. : Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program. 2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 25 October 2012.

2011

G. Roquier; R. Thavot; M. Mattavelli : Methodology For The Hardware/Software Co-Design Of Dataflow Programs. 2011. IEEE Workshop on Signal Processing Systems (SiPS), Beirut, LEBANON, Oct 04-07, 2011. p. 174-179. DOI : 10.1109/SiPS.2011.6088970.
G. Roquier; E. Benzati; M. Mattavelli; J. W. Janneck : Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs. 2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.
J. J. Ahmad; S. Li; I. Amer; M. Mattavelli : Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework. 2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121-130.
G. Roquier; E. Bezati; R. Thavot; M. Mattavelli : Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms. 2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.
E. Bezati; H. Yviquel; M. Raulet; M. Mattavelli : A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems. 2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.
C. Lucarz; M. Mattavelli; J. Janneck : Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011.
J. Ersfolk; G. Roquier; F. Jokhio; J. Lilius; M. Mattavelli : Scheduling of Dynamic Dataflow Programs with Model Checking. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011.
G. Roquier; R. Thavot; M. Mattavelli : Methodology for the Hardware/Software Co-Design of Dataflow Programs. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011.
A. Rahman; A. A. H. Bin; H. Amer; A. Prihozhy; C. Lucarz et al. : Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL. 2011. 2011 Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, November 2-4, 2011.
H. Amer; A. Rahman; A. A. H. Bin; I. Amer; C. Lucarz et al. : Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder. 2011. 2011 IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, October 4-7, 2011.

2010

A. Rahman; A. A. H. Bin; R. Thavot; M. Mattavelli; P. Faure : Hardware and Software Synthesis of Image Filters From CAL Dataflow Specification. 2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.
R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli : Automatic mutli-connectivity interface generation for system designs based on a dataflow description. 2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.
C. Lucarz; G. Roquier; M. Mattavelli : High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.
E. Bezati; M. Mattavelli; M. Raulet : RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, October 26-28, 2010.
F. Palumbo; D. Pani; E. Manca; L. Raffo; M. Mattavelli et al. : RVC: a Multi-Decoder CAL Composer tool. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.
J. W. Jannek; M. Mattavelli; M. Raulet; M. Wipliez : Reconfigurable Video Coding — a Stream Programming Approach to the Specification of New Video Coding Standards. 2010. MMSYS 2010, Phoenix, AZ, USA, Feb. 22-23, 2010.
B. Shao; D. Renzi; P. Amon; G. Xilouris; N. Zotos et al. : An adaptive system for real-time scalable video streaming with end- to-end qos control. 2010. The 11th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS), Desenzano del Garda, Italy, Apr 12 - 14, 2010.

2009

J. Boutellier; V. Martin Gomez; O. Silven; C. Lucarz; M. Mattavelli : Multiprocessor scheduling of dataflow models within the Reconfigurable Video Coding framework. 2009. Conference on Design and Architectures for Signal and Image Processing (DASIP), Sophia Antipolis, France, September 22 - 24, 2009.
J. Dubois; M. Mattavelli; J. Miteran; C. Lucarz; R. Mosqueron : Motion estimation accelerator with user search strategy for the RVC framework. 2009. IEEE International Conference on Image Processing, Cairo, Egypt, November 7-10, 2009.
H. Aman-Allah; E. Hanna; K. Maarouf; I. Amer : Towards a Comprehensive RVC VTL: A CAL Description of an Efficient AVC Baseline Encoder. 2009. IEEE International Conference on Image Processing, Special Session on Reconfigurable Video Coding, Cairo, Egypt, November 2009.
H. Aman-Allah; E. Hanna; K. Maarouf; I. Amer : An MPEG RVC AVC Baseline Encoder Based on a Novel Iterative Methodology. 2009. ECSI Conference on Design and Architectures for Signal and Image Processing, Sophia Antipolis, France, September 2009.
K. Maarouf; I. Amer : MPEG RVC Compliant Intra Prediction for AVC. 2009. ECSI Conference on Design and Architectures for Signal and Image Processing, Sophia Antipolis, France, September 2009.
H. Aman-Allah; I. Amer : AVC Entropy Coding for MPEG Reconfigurable Video Coding. 2009. ECSI Conference on Design and Architectures for Signal and Image Processing, Sophia Antipolis, France, September 2009.
I. Amer : Towards a Multi-Granular RVC VTL: A Case Study of CAL Transformations on the ISO/IEC MPEG Fixed Point IDCT. 2009. ECSI Conference on Design and Architectures for Signal and Image Processing, Sophia Antipolis,France, September 2009.
G. Roquier; C. Lucarz; M. Mattavelli; M. Wipliez; M. Raulet et al. : An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators. 2009. ISCAS 2009, Taipei, Taiwan, May, 2009. p. 799-799.
C. Lucarz; I. Amer; M. Mattavelli : Reconfigurable Video Coding : Objectives and Technologies. 2009. IEEE International Conference on Image Processing, Cairo, Egypt: 2009, Cairo, Egypt, 7-10 November, 2009. p. 749-752.

2008

C. Lucarz; M. Mattavelli; J. Dubois : A co-design platform for Algorithm/Architecture design exploration. 2008. IEEE International Conference on Multimedia & Expo, Hannover, Germany, June 23-26, 2008.
B. Shao; M. Mattavelli; D. Renzi; M. Andrade; S. Battista et al. : A Multimedia Terminal for Adaptation and End-to-end QoS Control. 2008. IEEE International Conference on Multimedia & Expo (ICME 2008), Hannover, Germany, June 23-26, 2008.
B. Shuvra; G. Brebner; J. Eker; J. Janneck; M. Mattavelli et al. : How to Make Stream Processing More Mainstream. 2008. Workshop on Streaming Systems: From Web and Enterprise to Multicore, in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Como, Italy, November 8, 2008.
C. Lucarz; M. Mattavelli; M. Wipliez; G. Roquier; M. Raulet et al. : Dataflow/Actor-Oriented language for the design of complex signal processing systems. 2008. Conference on Design and Architectures for Signal and Image Processing, DASIP 2008, Bruxelles, Belgium, 24-26 November 2008. p. 168-175.
J. Li; D. Ding; C. Lucarz; S. Keller; M. Mattavelli : Efficient Data Flow Variable Length Decoding Implementation for the MPEG Reconfigurable Video Coding Framework. 2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.
J. Boutellier; V. Sadhanala; C. Lucarz; P. Brisk; M. Marco Mattavelli : Scheduling Of Dataflow Models Within The Reconfigurable Video Coding Framework. 2008. Signal Processing Systems, 2008. SiPS 2008. IEEE Workshop on, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 182-187.
M. Raulet; J. Piat; C. Lucarz; M. Mattavelli : Validation of Bitstream Syntax and Synthesis of Parsers in the MPEG Reconfigurable Video Coding Framework. 2008. 2008 IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 1520-6130.
R. Thavot; R. Mosqueron; M. Alisafaee; C. Lucarz; M. Mattavelli et al. : Dataflow design of a co-processor architecture for image processing. 2008. Conference on Design and Architectures for Signal and Image Processing , DASIP 2008, Bruxelles, Belgium, 24-26 November 2008.
B. Shao; M. Mattavelli; D. Renzi; M. Andrade; S. Battista et al. : A Multimedia Terminal for Adaptation and End-to-end QoS Control. 2008. Proceedings of the IEEE International Conference on Multimedia & Expo (ICME 2008)., Hannover, Germany, 2008.
B. Shao; D. Renzi; M. Mattavelli; S. Battista; S. Keller : A Multimedia Terminal Supporting Adaptation for QoS Control. 2008. 9th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS 2008), Klagenfurt, Austria, May 7-9, 2008.
B. Shao; M. Mattavelli; M. Andrade; S. Keller; G. Ciobanu et al. : Multimedia Terminal Architecture: An Inter-Operable Approach. 2008. The First ACS/IEEE International Workshop on Wireless Internet Services (WISe'08) in conjunction with The Sixth ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-08), Doha, Qatar, April 1-4 2008.
R. Mosqueron; J. Dubois; M. Mattavelli : Smart camera with embedded co-processor: a postal sorting application. 2008. Optical and Digital Image Processing , Strasbourg, France , April 7 2008.

2007

R. Zhou; M. Mattavelli : A new time-frequency representation for music signal analysis: Resonator Time-Frequency Image. 2007. 9th International Symposium on Signal Processing and its Applications, Sharjah, U ARAB EMIRATES, Feb 12-15, 2007. p. 1278-1281.
J. Thomas-Kerr; J. Janneck; M. Mattavelli; I. Burnett; C. Ritz : Reconfigurable Media Coding: Self-Describing Multimedia Bitstreams. 2007. SIPS 2007, Shanghai, Oct. 17-19 2007.
R. Mosqueron; J. Dubois; M. Mattavelli : High Performance Embedded Co-Processor Architecture For CMOS Imaging Systems. 2007. Workshop on Design and Architectures for Signal and Image Processing, Grenoble (France), November 2007.
C. Lucarz; M. Mattavelli; J. Dubois : A HW/SW codesign platform for Algorithm-Architecture mapping. 2007. Workshop on Design and Architectures for Signal and Image Processing (DASIP), Grenoble, France, November 27-29.
C. Lucarz; M. Mattavelli : A platform for mixed HW/SW algorithm specifications for the exploration of SW and HW partitioning. 2007. PATMOS, Göteborg, Sweden, September 3-5, 2007. p. 485-494.
C. Lucarz; M. Mattavelli; J. Thomas-Kerr; J. Janneck : Reconfigurable media coding: a new specification model for multimedia coders. 2007. SiPS, Shanghai, China, October 17-19, 2007.

2006

B. Shao; L. Velazquez; N. Scaringella; N. Singh; M. Mattavelli : SMIL to MPEG-4 BIFS Conversion. 2006. The Second International Conference on Automated Production of Cross Media Content for Multi-Channel Distribution (AXMEDIS'06), Leeds, UK, December 13-15, 2006. p. 77-84. DOI : 10.1109/AXMEDIS.2006.49.

2005

J. Dubois; M. Mattavelli; L. Pierrefeu; J. Miteran : Configurable motion-estimation hardware accelerator module for the MPEG-4 reference hardware description platform. 2005. IEEE International Conference on Image Processing, ICIP 2005, Genova, September 11-14, 2005. p. 591-594.
P. Schumacher; M. Mattavelli; A. Chirila-Rus; R. Turney : A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs. 2005. ICME 2005, Amsterdam, July 6-8, 2005. p. 872-875.
P. Schumacher; M. Mattavelli; A. Chirila-Rus; R. Turney : A Software/Hardware Platform For Rapid Prototyping of Video and Multimedia Designs. 2005. IWSOC 2005, Banff, July 20-24, 2005. p. 30-33. DOI : 10.1109/IWSOC.2005.27.
M. Ravasi; M. Mattavelli : High Level Extraction of SoC Architectural Information from Generic C Algorithmic Descriptions. 2005. IWSOC, Banff, July 20-24, 2005.
M. Ravasi; M. Mattavelli : High-abstraction level complexity analysis and memory architecture simulations of multimedia algorithms. 2005. JFAAA'2005, Dijon, January 18-21, 2005. p. 673-684.
M. Lattuada; R. Posega; M. Mattavelli; D. Mlynek : Efficient error correction solutions for OFDM-based wireless video. 2005. IEEE, PRIME 2005 Conference, Ph.D. Research In Micro-Electronics & Electronics, Lausanne, July 25-28, 2005. p. 205-208.

2004

M. RAVASI; C. CLERC; M. MATTAVELLI; D. MLYNEK : An automatic tool for high-level algorithmic complexity evaluation and optimization for system design. 2004. Symposium on Design, Test, Integration and Packaging of MWMS/MOEMS, Montreux , SUISSE, May 12, 2004.

2003

A. Prihozhy; M. Mattavelli; D. Mlynek : Data Dependences Critical Path Evaluation at C/C++ System Level. 2003. p. 569-5792003.
M. Ravassi; M. Mattavelli; P. Schumacher; R. Turney : High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder. 2003.
J. Dubois; M. Mattavelli : Embedded co-processor architecture for CMOS based image acquisition. 2003. International Conference on Image Processing, ICIP 2003, Barcelona, September 14-17, 2005. p. 591-594.

2002

A. Prihozhy; D. Mlynek; M. Solomennik; M. Mattavelli : Techniques for Optimization of Net Algorithms. 2002. International Conference on Parallel Computing in Electrical Engineering, PARALEC'02, Warsaw, September 22-25, 2002. p. 211-216.
C. Alberti; A. Romeo; M. Mattavelli; D. Mlynek : An interpreted approach to multimedia streams protection. 2002. Eusipco 2002, Toulouse, September 2002. p. 63-66.

2001

G. Zoia; C. Alberti : An MPEG-oriented platform for Wave Field Synthesis Arrays of Loudspeakers. 2001.
G. Zoia; C. Alberti : An Audio Virtual DSP for Multimedia Frameworks. 2001.
J. Lafitte; D. Mlynek : Paradys: A scalable Infrastructure for parallel circuit simulation. 2001.

2000

G. Zoia; C. Alberti : An Efficient Block-Based Interpreter for MPEG-4 Structured Audio. 2000.
M. Ravasi; M. Mattavelli; D. Mlynek : Scheduling Strategies for 2D Wavelet Coding Implementations. 2000.
E. Juarez; M. Mattavelli; D. Mlynek : A System-on-a-chip for Multimedia Stream Processing & Communication. 2000.
A. Romeo; M. Mattavelli : A Hardware Oriented Analysis of Cryptographic Systems for Multimedia Applications. 2000.
G. Zoia; C. Alberti : A virtual DSP Architecture for MPEG-4 structured Audio. 2000.

1999

L. Le Bourhis; G. Zoia; M. Mattavelli; D. Mlynek : An efficient Host/Co-Processor Solution for MPEG-4 Audio Composition. 1999. p. 26-27.
A. Romeo; G. Romolotti; M. Mattavelli; D. Mlynek : Very high throughput Crypto-System Architectures: The RPK Solution. 1999. International Conference on Consumer Electronics, Los Angeles, June 22-24, 1999. p. 96-97.
M. Ravasi; M. Mattavelli; D. Mlynek; A. Buttar; S. Sondagar : Wavelet Image Compression for mobile/portable Application. 1999. International Conference on Consumer Electronics, Los Angeles, June 22-24, 1999. p. 374-375.
A. Romeo; G. Romolotti; M. Mattavelli; D. Mlynek : Cryptosystem architectures for very high throughput multimedia encryption. 1999. September 5-8, 1999. p. 261-264.

1998

M. Mattavelli; V. Noel; E. Amaldi : An efficient line detection algorithm based on a new combinatorial optimization formulation. 1998.
M. Mattavelli; G. Zoia : Vector Tracing Techniques for Motion Estimation Algorithms in Video Coding. 1998. p. 2097-2100.
M. Mattavelli; G. Zoia : An Efficient Motion Estimation Algorithm Based on Tracing Techniques on Large Search Windows. 1998.
G. Zoia : New Audio Applications for Multimedia and MPEG-4: Complexity and Hardware. 1998.

1997

M. Mattavelli; S. Brunetton; D. Mlynek : A Parallel Multimedia Processor for Macroblok Based Compression Standars. 1997. p. 570-573.
M. Mattavelli; S. Brunetton; D. Mlynek : Computational Graceful Degradation for Video Sequence Ddecoding. 1997.
L. Chaouat; S. Garin; A. Vachoux; D. Mlynek : Rapid Prototyping of Hardware Systems via Model Reuse. 1997.
S. Dogimont; M. Gumm; F. Mombers : Conception And Design Of A RISC CPU For The Use As Embedded Controller Within A Parallel Multimedia Architecture. 1997.
F. Mombers; D. Nicoulaz; M. Gumm; S. Dogimont; F. Bellifemmine : A Video Signal Processor Core for Motion Estimation in MPEG2 Encoding. 1997.
M. Gumm; M. Brocci; F. Mombers : A High Fault-Coverage Design-for-Testability Approach for a MIMD Based Multimedia Processor. 1997.
L. Chaouat; A. Schmid; A. Vachoux; D. Mlynek : Case-Based Synthesis of Telecommunication Architectures. 1997.

1996

L. Chaouat; A. Schmid; A. Vachoux; D. Mlynek : Generating Telecommunication Architectures in the Mentor Graphics DSP Station Environment. 1996.
L. Chaouat; A. Vachoux; D. Mlynek : A Method to Implement a Knowledge-Based system for Fast Prototyping of Hardware Designs. 1996. p. 71-76.

1995

L. Chaouat; C. Munk; A. Vachoux; D. Mlynek : An Expert Assistant for Hardware Systems Specification. 1995. p. 59-75.

1993

R. Hervigo : Traitement en temps reel d'algorithmes pour l'estimation de mouvement. 1993.

R. Thavot; R. Mosqueron; J. Dubois; M. Mattavelli : Hardware synthesis of complex standard interfaces using CAL dataflow descriptions. DASIP, Sophia Antipolis, September 22-24, 2009.
D. Ding; L. Yu; C. Lucarz; M. Mattavelli : Video Decoder Reconfigurations and AVS Extensions in the New MPEG Reconfigurable Video Coding Framework. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.
J. Boutellier; V. Sadhanala; C. Lucarz; P. Brisk; M. Mattavelli : Scheduling Of Dataflow Models Within The Reconfigurable Video Coding Framework. IEEE Workshop on Signal Processing Systems. SiPS 2008. , Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.
M. Raulet; J. Piat; C. Lucarz; M. Mattavelli : Validation of Bitstream Syntax and Synthesis of Parsers in the MPEG Reconfigurable Video Coding Framework. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.
S. Bhattacharyya; G. Brebner; J. Eker; J. Janneck; M. Mattavelli et al. : OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems. First Swedish Workshop on Multi-Core Computing, MCC, Ronneby, Sweden, November 27-28, 2008.
J. W. Janneck; I. D. Miller; D. B. Parlour; M. Mattavelli; C. Lucarz et al. : Translating Dataflow Programs to Efficient Hardware: an MPEG-4 Simple Profile Decoder Case Study. Design, Automation and Test in Europe (DATE), Munich, Germany, 2008.

Books

2001

A. Prihozhy; L. Prihozhaya : Methods of Partial Logic for Knowledge Representation & Deductive Reasoning in Incompletely Specified Domains ; Boston/Dordrecht/London: Kluwer Academic Publishers.

Theses

2017

M. M. Michalska / M. Mattavelli (Dir.) : Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms. Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7607.

2015

S. Casale-Brunet / M. Mattavelli (Dir.) : Analysis and optimization of dynamic dataflow programs. Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6663.
E. Bezati / M. Mattavelli (Dir.) : High-level synthesis of dataflow programs for heterogeneous platforms. Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6653.

2014

A. A. H. B. Ab Rahman / M. Mattavelli (Dir.) : Optimizing Dataflow Programs for Hardware Synthesis. Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.

2011

C. Lucarz / M. Mattavelli (Dir.) : Dataflow Programming for Systems Design Space Exploration for Multicore Platforms. Lausanne, EPFL, 2011. DOI : 10.5075/epfl-thesis-5069.

2009

B. Shao / M. Mattavelli (Dir.) : Adaptation based scalable video delivery and management. Lausanne, EPFL, 2009. DOI : 10.5075/epfl-thesis-4550.

2007

S. Aguirre / D. Mlynek; M. Mattavelli (Dir.) : Deep-submicron embedded processor architectures for high-performance, low-cost and low-power. Lausanne, EPFL, 2007. DOI : 10.5075/epfl-thesis-3742.
C. Clerc / M. Mattavelli (Dir.) : A profiling framework for high level design space exploration for memory and system architectures. Lausanne, EPFL, 2007. DOI : 10.5075/epfl-thesis-3706.

2006

R. Zhou / M. Mattavelli (Dir.) : Feature extraction of musical content for automatic music transcription. Lausanne, EPFL, 2006. DOI : 10.5075/epfl-thesis-3638.

2005

R. Posega / D. Mlynek (Dir.) : Advanced OFDM systems for terrestrial multimedia links. Lausanne, EPFL, 2005. DOI : 10.5075/epfl-thesis-3220.
M. Lattuada / D. Mlynek (Dir.) : Efficient error correction solutions for OFDM based digital video. Lausanne, EPFL, 2005. DOI : 10.5075/epfl-thesis-3154.

2004

M. Epalza / D. Mlynek (Dir.) : Adding limited reconfigurability to superscalar processors. Lausanne, EPFL, 2004. DOI : 10.5075/epfl-thesis-3124.
A. Simeonov / D. Mlynek (Dir.) : A flexible framework for efficient design of advanced 3D audio systems in multimedia applications. Lausanne, EPFL, 2004. DOI : 10.5075/epfl-thesis-3094.
C. Alberti / D. Mlynek (Dir.) : Intellectual property management and protection for multimedia content. Lausanne, EPFL, 2004. DOI : 10.5075/epfl-thesis-3028.
F. Font Torre de Mer / D. Mlynek (Dir.) : A multiple core mode for protocol independent multicast. Lausanne, EPFL, 2004. DOI : 10.5075/epfl-thesis-3027.
A. Romeo / D. Mlynek (Dir.) : Reactive security for multimedia systems. Lausanne, EPFL, 2004. DOI : 10.5075/epfl-thesis-3005.

2003

M. Ravasi / D. Mlynek (Dir.) : An automatic C-code instrumentation framework for high level algorithmic complexity analysis and system design. Lausanne, EPFL, 2003. DOI : 10.5075/epfl-thesis-2839.
E. Juarez / D. Mlynek (Dir.) : Contribution to the design of distributed virtual-time based scheduling algorithms. Lausanne, EPFL, 2003. DOI : 10.5075/epfl-thesis-2789.
B. Mota / D. Mlynek (Dir.) : Time-domain signal processing algorithms and their implementation in the ALTRO chip for the ALICE TPC. Lausanne, EPFL, 2003. DOI : 10.5075/epfl-thesis-2767.

2002

F. A. Cherigui / D. Mlynek (Dir.) : High performance VLSI architectures implementing strong cryptographic primitives. Lausanne, EPFL, 2002. DOI : 10.5075/epfl-thesis-2561.

2001

G. Zoia / D. Mlynek (Dir.) : A virtual model for simulation and design of architectures in MPEG-4 audio and multimedia context. Lausanne, EPFL, 2001. DOI : 10.5075/epfl-thesis-2362.

2000

F. Mombers / D. Mlynek (Dir.) : Specification and integration of new multimedia processor architectures with emphasis on critical motion estimation algorithms implementation. Lausanne, EPFL, 2000. DOI : 10.5075/epfl-thesis-2162.
A. Schmid / D. Mlynek (Dir.) : VLSI realization of mixed analog-digital artificial neural networks dedicated to autonomous systems with on-chip learning capability. Lausanne, EPFL, 2000. DOI : 10.5075/epfl-thesis-2101.

1999

J. T. Randriamalazarivo / D. Mlynek (Dir.) : HAWK: an open error-control and cryptographic V-VLIW processor for digital communication techniques and storage. Lausanne, EPFL, 1999. DOI : 10.5075/epfl-thesis-2013.
M. Gumm / D. Mlynek (Dir.) : On VLSI architectures for motion estimation in high quality video compression systems. Lausanne, EPFL, 1999. DOI : 10.5075/epfl-thesis-1956.

1998

P. Duc / D. Mlynek (Dir.) : A VLSI processor architecture for professional digital audio. Lausanne, EPFL, 1998. DOI : 10.5075/epfl-thesis-1774.

1997

L. Chaouat / D. Mlynek (Dir.) : A design environment for knowledge-guided specification of hardware systems via model reuse. Lausanne, EPFL, 1997. DOI : 10.5075/epfl-thesis-1670.
M. Mattavelli / M. Kunt (Dir.) : Motion analysis and estimation. Lausanne, EPFL, 1997. DOI : 10.5075/epfl-thesis-1596.

1996

D. Nicoulaz / D. Mlynek (Dir.) : A parallel VLSI architecture optimized for block-based image processing. Lausanne, EPFL, 1996. DOI : 10.5075/epfl-thesis-1562.

1995

R. Hervigo / D. Mlynek (Dir.) : V.L.S.I. dédiées à la recherche de similitudes. Lausanne, EPFL, 1995. DOI : 10.5075/epfl-thesis-1331.
C. Munk / D. Mlynek (Dir.) : A methodology for designing and using a hardware system specification environment. Lausanne, EPFL, 1995. DOI : 10.5075/epfl-thesis-1309.

1994

L. Lemaitre / D. Mlynek (Dir.) : Theoretical aspects of the VLSI implementation of fuzzy algorithms. Lausanne, EPFL, 1994. DOI : 10.5075/epfl-thesis-1226.
J. Kowalczuk / D. Mlynek (Dir.) : On the design and implementation of algorithms for muti-media systems. Lausanne, EPFL, 1994. DOI : 10.5075/epfl-thesis-1188.

Book Chapters

2011

M. Mattavelli : MPEG Reconfigurable Video Representation; The MPEG Representation of Digital Media; Springer, 2011.

2010

R. Thavot; R. Mosqueron; J. Dubois; M. Mattavelli : Generation of Hardware/Software Systems Based on CAL Dataflow Description; Algorithm-Architecture Matching for Signal and Image Processing; http://www.springer.com/engineering/signals/book/978-90-481-9964-8?changeHeader: Springer, 2010. p. 275-292.
M. Mattavelli; J. W. Janneck; M. Raulet : MPEG Reconfigurable Video Coding; Handbook of Signal Processing Systems,; Springer, 2010. p. 43-67.

Working Papers

2008

D. Ding; C. Lucarz; M. Mattavelli; L. Yu : [ISO/IEC MPEG contribution] Function Units for Conversion from Syntax to Sequence of Tokens: BTYPE. 2008.
C. Lucarz; J. Li; M. Mattavelli; D. Ding : [ISO/IEC MPEG contribution] Functional Units for RVC Toolbox: Variable Length Decoding. 2008.
C. Lucarz; J. Li; M. Mattavelli; D. Ding : [ISO/IEC MPEG contribution] Auto-generation of RVC Parser from BSDL Syntax Description: Variable Length Decoding. 2008.
C. Lucarz; D. Ding; J. Li; M. Mattavelli : [ISO/IEC MPEG contribution] BSDL Description of MPEG-4 SP and AVC BP Bitstream Syntax for RVC Framework. 2008.
D. Ding; M. Mattavelli; C. Lucarz; L. Yu : [ISO/IEC MPEG contribution] Update of Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework. 2008.

2007

C. Lucarz; J. Thomas-Kerr; M. Mattavelli; J. Janneck; D. Parlour et al. : [ISO/IEC MPEG contribution] Implement flexible FUs according to the processing mechanism in CVC WD using CAL (Results of Core Experiment 1.1) and analysis of the compactness of RVC Abstract Decoder Model (Results of Core Experiment 1.3). 2007.
D. Ding; M. Mattavelli; C. Lucarz; L. Yu : [ISO/IEC MPEG contribution] Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework. 2007.
C. Lucarz; J. Thomas-Kerr; M. Mattavelli : [ISO/IEC MPEG contribution] A systematic procedure for the generation of a CAL parser from BDSL in the RVC framework - result CE 1.1. 2007.
C. Lucarz; M. Mattavelli; D. Parlour : [ISO/IEC MPEG contribution] Serialized version of some MPEG-4 SP FUs. 2007.
C. Lucarz; J. Thomas-Kerr; M. Mattavelli : [ISO/IEC MPEG contribution] Reconfigurability potential of the MPEG-4 SP decoder (results of CE 1.1). 2007.
C. Lucarz; M. Mattavelli : [ISO/IEC MPEG contribution] Implementation of multiple reference frame support in RVC CAL model. 2007.
C. Lucarz; M. Mattavelli : [ISO/IEC MPEG contribution] Compression of the RVC DDL Decoder Description with BiM (results of Core Experiment 1.3 in RVC). 2007.
C. Lucarz; M. Mattavelli; A. Kinane; S. Lee; S. Lee : [ISO/IEC MPEG contribution] RVC Functional Units naming process proposal. 2007.
M. Mattavelli; C. Lucarz; A. Kinane; K. Radha; J. Janneck et al. : [ISO/IEC MPEG contribution] Update of the Textual specification of Functional Units, DDL and FUs SW of the MPEG-4 SP RVC Abstract Decoder Model (Results of CE 2.1). 2007.
C. Lucarz; M. Mattavelli; A. Kinane; R. Krisha : [ISO/IEC MPEG contribution] A proposal for the classification and mapping of MPEG video coding technology into Functional Units for the RVC framework (Results of CE 2.2). 2007.

2006

M. Mattavelli; A. Kinane; C. Lucarz; J. Janneck; D. Parlour : [ISO/IEC MPEG contribution] Report on results of RVC CE 2.1 Reshape the current MPEG-4 SP CAL decoder according to the current FU interface in RVC WM. 2006.
C. Lucarz; M. Mattavelli; A. Kinane : [ISO/IEC MPEG contribution] Report on results of RVC CE 2.2: Explore the extensibility of FUs. 2006.

Reports

1999

X. Peillon; H. Teodorescu : Analysis of Chaos Sensitivity in Circuits Baseed on Wien Oscillators. 1999.

1995

A. Basso; M. Mattavelli; Y. Pustzaszeri; J. Hubaux : Remote teaching by multimedia communications: the BETEL project. 1995.

Posters

2018

A. A. Hernandez Lopez : Transcriptome reconstruction with quality score distortion in reference-based alignment ; Research in computational molecular biology (RECOMB), Paris, France, April 19-24, 2018.

2008

J. W. Janneck; I. D. Miller; D. B. Parlour; M. Mattavelli; C. Lucarz et al. : Translating Dataflow Programs to Efficient Hardware: an MPEG-4 Simple ProfileDecoder Case Study ; Design, Automation and Test in Europe (DATE08), Munich, Germany.

Talks

2004

M. Ravasi : An Automatic C code Instrumentation Framework for High Level Algorithmic Complexity Analysis and System Design ; EDAA Ph.D. Forum, Design Automation and Test in Europe 2004 (DATE 2004), Paris, France, February 16 to 20, 2004.

Student Projects

2010

R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli : Automatic mutli-connectivity interface generation for system designs based on a dataflow description ; 2010.
A. Rahman; A. Al-Hadi; R. Thavot; M. Mattavelli; P. Faure : Hardware and software synthesis of image filters from CAL dataflow specification ; 2010.