Publications 2014

S. Casale Brunet; M. Michalska; E. Bezati; M. Mattavelli; J. Janneck et al. : TURNUS: an open-source design space exploration framework for dynamic stream programs. 2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014.
M. Canale; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck : Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, October 2014.
S. Casale Brunet; E. Bezati; M. Mattavelli; M. Canale; J. Janneck : Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014. DOI : 10.1109/DASIP.2014.7115623.
D. J. De Saint Jorre; D. Renzi; S. Casale Brunet; M. Michalska; E. Bezati et al. : MPEG high efficient video coding stream programming and many-cores scalability. 2014.
S. Casale-Brunet; M. Wiszniewska; E. Bezati; M. Mattavelli; J. W. Janneck et al. : TURNUS: An open-source design space exploration framework for dynamic stream programs. 2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.
S. Casale-Brunet; E. Bezati; M. Mattavelli; M. Canale; J. W. Janneck : Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.
E. Bezati; S. Casale Brunet; M. Mattavelli; J. W. Janneck : Coarse grain clock gating of streaming applications in programmable logic implementations. 2014. 2014 Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, 31 May - 1 June 2014. p. 1-6. DOI : 10.1109/ESLsyn.2014.6850387.
J. W. Janneck; S. Casale-Brunet; M. Mattavelli : Characterizing communication behavior of dataflow programs using trace analysis. 2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.
D. De Saint Jorre; C. Alberti; M. Mattavelli; S. Casale-Brunet : Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms. 2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.
J. W. Janneck; G. Cerdersjo; E. Bezati; S. C. Brunet : Dataflow machines. 2014. 2014 48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 2-5 November 2014. p. 1848-1852. DOI : 10.1109/ACSSC.2014.7094788.
M. Canale; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. W. Janneck : Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.
C. Sau; L. Raffo; F. Palumbo; E. Bezati; S. Casale-Brunet et al. : Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. 2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations. 2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014.
A. A.-H. Ab Rahman; S. Casale-Brunet; C. Alberti; M. Mattavelli : A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations. 2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.
J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. : ECMA-407: A New 3D audio codec implementation up to NHK 22.2. 2014. The 28th VDT International Convention 2014.
J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. : ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL. 2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.
M. Canale; S. Casale-Brunet : A Multidisciplinary Approach for Model Predictive Control Education: A Lego Mindstorms NXT-based Framework; International Journal Of Control Automation And Systems. 2014. DOI : 10.1007/s12555-013-0282-7.
A. A. H. B. Ab Rahman / M. Mattavelli (Dir.) : Optimizing Dataflow Programs for Hardware Synthesis. Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.
E. Bezati; R. Thavot; G. Roquier; M. Mattavelli : High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms; Journal Of Real-Time Image Processing. 2014. DOI : 10.1007/s11554-013-0326-5.